SUE - Design Environment

SUE is a graphical environment that allows users to enter, visualize, and control large, complex chip designs. SUE is the first tool to combine HDL-based functional designs with structural design. SUE understands everything from Verilog down to the operation and physical placement of transistors and wires.

DataPath Compiler (DPC)

Allows the user to generate data paths from a schematic view, and back annotate accurate timing information onto the schematic in seconds. DPC can place custom-style "bit slice" data paths minimizing wire lengths for high performance, and can even include control logic, all using your existing standard cell library.

MAX is an extremely fast, industrial strength, full-custom layout editor with the added benefit of a complete Tcl/Tk interface and API. MAX comes with continuous DRC, connectivity tracing, schematic cross-probing, wiring tool, extraction, schematic-driven layout, and more. MAX reads and writes GDSII and LEF/DEF.

MAX-LS seamlessly integrates the schematic capture of SUE with the MAX layout editor to provide true, schematic-driven physical layout. It includes interactive cell generation based on LVS and DRC correct layout, and can handle the largest SoC IC design databases. Its GDSII output can go directly to mask composition products for IC fabrication.

MegaCell Compiler (MCC)

The Mega Cell Compiler (MCC) allows users to easily build their own generators for SRAM's, DRAM's, ROM's, pad rings or any other regular or semi-regular structure, in just minutes. Verilog, HSPICE, critical path netlists, and timing models can all be generated automatically.